1. Field of the Invention
The present invention relates to a method for driving a plasma display panel (PDP) of a surface discharge format and a display apparatus.
A PDP is commercialized as a wall-hung TV set or a monitor display of a computer, and the screen size thereof has reached 60 inches. In addition, PDP is a digital display device made of binary light emission cells, so it is suitable for a display of digital data and is expected as a multimedia monitor. In order to respond the market request and to promote a large size and a high definition, it is necessary to develop a panel structure as well as a driving method.
2. Description of the Prior Art
An AC type PDP for a color display employs a surface discharge format. The surface discharge format has an arrangement of electrodes in which display electrodes that become anodes and cathodes in a display discharge for ensuring a luminance are arranged in parallel on a front or back substrate, and address electrodes are arranged so as to cross a pair of the display electrodes. In the surface discharge format PDP, a partition is necessary for separating a discharge space for each column of a matrix display along the longitudinal direction of the display electrode (hereinafter referred to as the row direction). As the simplest partition pattern having good productivity, a so-called stripe pattern is known in which a linear band-like partition in a plan view is arranged at each boundary between columns.
There are two kinds of arrangements of display electrodes in the surface discharge format. In one arrangement, a pair of display electrodes is arranged for each row. The total number of the display electrodes is twice the number of rows n. In this format each row is independent of other rows, so the driving sequence can be simplified. However, in the case of the stripe pattern, an electrode gap between neighboring rows (referred to as a reverse slit) should be sufficiently large value, e.g., several times an arrangement interval (a surface discharge gap length) so as to prevent an interference of discharge between rows. In the other arrangement, display electrodes whose number is the number of rows n plus one are arranged substantially at the constant pitch. In this format, neighboring display electrodes constitute an electrode pair for a surface discharge, and each display electrode except for the both ends of the arrangement works for both displays of an odd row and an even row. From the viewpoint of a high definition (a fine pitch of rows) and effective usage of a display surface, the arrangement at a constant pitch is advantageous.
In a display, regardless of the arrangement format of display electrodes, an address discharge is generated between one electrode of the display electrode pair corresponding to each row and the address electrode, and a discharge is generated between display electrodes using the address discharge as a trigger, so that a charge quantity in a dielectric (a wall charge quantity) is controlled for addressing in accordance with a display content. After the addressing, a sustaining voltage Vs having alternating polarity is applied to the display electrode pair. The sustaining voltage Vs satisfies the inequality (1).VfXY−VWXY<Vs<VfXY  (1)
Here, VfXY is a discharge starting voltage between display electrodes, and VWXY is a wall voltage between display electrodes.
By applying the sustaining voltage Vs, a cell voltage (a sum of a driving voltage applied to an electrode and a wall voltage) exceeds the discharge starting voltage VfXY only in the cell having a predetermined quantity of wall charge, so that a surface discharge is generated along a substrate surface. If the application period is shortened, the light emission looks continuous.
FIG. 20 shows waveforms of cell voltage during the address period in the conventional driving method. In the address period TA, one electrode of the display electrode pair (i.e., a display electrode Y) is used as a scanning electrode for row selection in a screen having n rows and m columns. Display electrodes except for the scanning electrodes are display electrodes X. At the starting point of the address period TA, all display electrodes Y are biased to the non-selecting potential Vya′, and all display electrodes X are biased to a predetermined potential Vxa′ for preventing misdischarge. After that, the display electrode Yj corresponding to the selected row j (1≦j≦n) is temporarily biased to the selecting potential Vy′ (application of a scanning pulse).
In synchronization with the row selection, the address electrode A of the row to which the selected cell belongs that generates the address discharge among the selected row is biased to the selecting potential Va′ (application of an address pulse). In FIG. 20, the row k is shown as a typical row, and the address electrode Ak is biased to the selecting potential Va′ in the selected period of each row (j−1), j or (j+1). The bias potential Vxa′ of the display electrode Xj is set so that the cell voltage of the interelectrode XY is a little lower than the discharge starting voltage VfXY when the scanning pulse is applied to the display electrode Yj. Thus, when an address discharge is generated at the interelectrode AY between the address electrode Ak and the display electrode Yj, the address discharge causes a discharge (hereinafter referred to as an address discharge for convenience's sake) at the interelectrode XY. The address discharge is not generated at the interelectrode XY of the non-selected cell having not trigger. Typical voltage setting is as follows.
The bias potential Vxa′ of the display electrode X is 80-90 volts.
The selecting potential Vy′ (the amplitude of the scanning pulse) is −170 volts.
The selecting potential Va′ (the amplitude of the address pulse) is 60-70 volts.
In the conventional driving method, the cell-selecting voltage Vay′ applied to the interelectrode AY by the scanning pulse and the address pulse is set to the value (230-240 volts) higher than the discharge starting voltage VfAY of the interelectrode AY regardless of the potential of the display electrode X, so that an address discharge is generated at the interelectrode AY. Namely, the addressing is performed in which a cell is selected by controlling potentials of two kind electrodes (the display electrode Y and the address electrode A) out of three kinds electrodes.
As explained above, in a PDP having a structure of display electrodes that are arranged at a constant pitch, one display electrode is commonly used by both displays of an odd row and an even row, so the display format is limited to an interlaced format. In the interlaced format, a half of the total rows are not used for display of each field. For example, even rows do not emit light in odd fields. Therefore, luminance of the display becomes lower than the progressive format. Especially, if the partition pattern is a grid pattern that can prevent the interference of discharge securely, the light emission area of each cell becomes narrower than in the case of the stripe pattern, so the non-light emission area in the screen increases. If the display is performed in which display data of one row are adapted to two rows in each field for increasing the luminance, the resolution in the column direction is reduced by half. Furthermore, the interlaced format can hardly satisfy a display quality that is required to high-resolution equipment such as a DVD or a full-specification HDTV, since a flicker is generated in a still picture display.